SH7201 Datasheet, PDF (798/1196 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 18 Serial Sound Interface (SSI)
18.3 Register Description
The SSI has the following registers. Note that explanation in the text does not refer to the
channels.
Table 18.2 Register Description
Channel Register Name
Abbreviation R/W Initial Value Address
Access
Size
0
Control register 0
SSICR0
R/W H'00000000 H'FFFED000 32
Status register 0
SSISR0
R/W* H'02000003 H'FFFED004 32
Transmit data register 0 SSITDR0
R/W H'00000000 H'FFFED008 32
Receive data register 0 SSIRDR0
R
H'00000000 H'FFFED00C 32
1
Control register 1
SSICR1
R/W H'00000000 H'FFFED080 32
Status register 1
SSISR1
R/W* H'02000003 H'FFFED084 32
Transmit data register 1 SSITDR1
R/W H'00000000 H'FFFED088 32
Receive data register 1 SSIRDR1
R
H'00000000 H'FFFED08C 32
Note: * For this register, bits 26 and 27 are capable of reading and writing, although the others
are read-only bits. For details, refer to section 18.3.2, Status Register (SSISR).
Rev. 2.00 Sep. 07, 2007 Page 770 of 1164
REJ09B0321-0200