SH7201 Datasheet, PDF (152/1196 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 6 Interrupt Controller (INTC)
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
— — — — — — — — IRQ7F IRQ6F IRQ5F IRQ4F IRQ3F IRQ2F IRQ1F IRQ0F
Initial value: 0
0
0
0
0
0
0
0
R/W: R R R R R R R R
Note: * Only 0 can be written to clear the flag after 1 is read.
0
0
0
0
0
0
0
0
R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)*
Bit
15 to 8
Bit Name

7
IRQ7F
6
IRQ6F
5
IRQ5F
4
IRQ4F
3
IRQ3F
2
IRQ2F
1
IRQ1F
0
IRQ0F
[Legend]
n = 7 to 0
Initial
Value
All 0
0
0
0
0
0
0
0
0
R/W Description
R
Reserved
These bits are always read as 0. The write value
should always be 0.
R/(W)* ^{IRQ Interrupt Request}
R/(W)* ^{These bits indicate the status of the IRQ7 to IRQ0}
interrupt requests.
R/(W)*
R/(W)* ^{Level detection:}
R/(W)* ^{0: IRQn interrupt request has not occurred}
R/(W)* ^{[Clearing condition]}
R/(W)* ^{• IRQn input is high}
R/(W)* 1: IRQn interrupt has occurred
[Setting condition]
• IRQn input is low
Edge detection:
0: IRQn interrupt request is not detected
[Clearing conditions]
• Cleared by reading IRQnF while IRQnF = 1, then
writing 0 to IRQnF
• Cleared by executing IRQn interrupt exception
handling
1: IRQn interrupt request is detected
[Setting condition]
• Edge corresponding to IRQn1S or IRQn0S of
ICR1 has occurred at IRQn pin
Rev. 2.00 Sep. 07, 2007 Page 124 of 1164
REJ09B0321-0200