SH7201 Datasheet, PDF (88/1196 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 2 CPU
2.5 Processing States
The CPU has four processing states: reset, exception handling, program execution, and power-
down. Figure 2.6 shows the transitions between the states.
Manual reset from any state
Power-on reset from any state
Manual reset state
Reset canceled
Power-on reset state
Reset state
Interrupt source or
DMA address error occurs
Exception
handling state
Exception
handling
source
occurs
Exception
handling
ends
Program execution state
NMI interrupt or
IRQ interrupt occurs
NMI interrupt,
IRQ interrupt*,
Manual reset,
and Power-on reset
STBY bit cleared
for SLEEP
instruction
STBY bit set
and DEEP bit clear
for SLEEP
instruction
STBY and DEEP bits set
for SLEEP
instruction
Sleep mode
Software standby mode
Deep standby mode
Note: * IRQ can be released only by PE7 to PE4 and PC25 to PC22
Power-down state
Figure 2.6 Transitions between Processing States
Rev. 2.00 Sep. 07, 2007 Page 60 of 1164
REJ09B0321-0200