SH7201 Datasheet, PDF (719/1196 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 16 Serial Communication Interface with FIFO (SCIF)
Table 16.4 Bit Rates and SCBRR Settings (Asynchronous Mode) (4)
Pφ (MHz)
20
24
24.576
Bit Rate
Error
Error
Error
(bit/s)
n N (%) n N (%) n N (%) n
110
3 88 –0.25 3 106 –0.44 3 108 0.08 3
150
3 64 0.16 3 77 0.16 3 79 0.00 3
300
2 129 0.16 2 155 0.16 2 159 0.00 2
600
2 64 0.16 2 77 0.16 2 79 0.00 2
1200
1 129 0.16 1 155 0.16 1 159 0.00 1
2400
1 64 0.16 1 77 0.16 1 79 0.00 1
4800
0 129 0.16 0 155 0.16 0 159 0.00 0
9600
0 64 0.16 0 77 0.16 0 79 0.00 0
19200
0 32 –1.36 0 38 0.16 0 39 0.00 0
31250
0 19 0.00 0 23 0.00 0 24 –1.70 0
38400
0 15 1.73 0 19 –2.34 0 19 0.00 0
28.7
Error
N (%)
126 0.31
92 0.46
186 –0.08
92 0.46
186 –0.08
92 0.46
186 –0.08
92 0.46
46 –0.61
28 –1.03
22 1.55
Table 16.4 Bit Rates and SCBRR Settings (Asynchronous Mode) (5)
Pφ (MHz)
30
33
36
Bit Rate
(bit/s) n N
Error
(%) n N
Error
Error
(%) n N (%) n
110
3 132 0.13 3 145 0.33 3 159 –0.12 3
150
3 97 –0.35 3 106 0.39 3 116 0.16 3
300
2 194 0.16 2 214 –0.07 2 233 0.16 2
600
2 97 –0.35 2 106 0.39 2 116 0.16 2
1200 1 194 0.16 1 214 –0.07 1 233 0.16 1
2400 1 97 –0.35 1 106 0.39 1 116 0.16 1
4800 0 194 –1.36 0 214 –0.07 0 233 0.16 0
9600 0 97 –0.35 0 106 0.39 0 116 0.16 0
19200 0 48 –0.35 0 53 –0.54 0 58 –0.69 0
31250 0 29 0.00 0 32 0.00 0 35 0.00 0
38400 0 23 1.73 0 26 –0.54 0 28 1.02 0
Note: Settings with an error of 1% or less are recommended.
38
40
Error
Error
N (%) n N (%)
168 –0.19 3 177 –0.25
123 –0.24 3 129 0.16
246 0.16 3 64 0.16
123 –0.24 2 129 0.16
246 0.16 2 64 0.16
123 –0.24 1 129 0.16
246 0.16 1 64 0.16
123 –0.24 0 129 0.16
61 –0.24 0 64 0.16
37 0.00 0 39 0.00
30 –0.24 0 32 –1.36
Rev. 2.00 Sep. 07, 2007 Page 691 of 1164
REJ09B0321-0200