SH7201 Datasheet, PDF (1128/1196 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 28 List of Registers
Register
Power-on
Abbreviation Reset
Manual
Reset
Software
Standby
Deep
Standby
Module
Standby
Sleep
Module
MB[0 to 15]. Initialized
MSG_DATA[7]
Retained
Initialized
Initialized*¹ Retained
Retained
RCAN-ET
MB[0 to 15]. Initialized
CONTROL1H
Retained
Initialized
Initialized*¹ Retained
Retained
MB[0 to 15]. Initialized
CONTROL1L
Retained
Initialized
Initialized*¹ Retained
Retained
DREQER0
Initialized
Retained
Retained
Initialized*¹ 
Retained
INTC
DREQER1
Initialized
Retained
Retained
Initialized*¹ 
Retained
DREQER2
Initialized
Retained
Retained
Initialized*¹ 
Retained
DREQER3
Initialized
Retained
Retained
Initialized*¹ 
Retained
DSFR
Initialized
Retained
Retained
Retained

Retained
SYSTEM
DSCNT
Initialized
Retained
Retained
Initialized*¹ 
Retained
RAMKP
Initialized
Retained
Retained
Initialized*¹ 
Retained
Notes: 1. Not initialized in deep standby mode. But initialized after deep standby mode is
released because a power-on reset exception handling is executed.
2. Initialized by UDTRST assertion or in the Test-Logic-Reset state of the TAP controller.
3. Bits BN[3:0] are initialized.
4. Retains the previous value after an internal power-on reset by means of the WDT.
5. Counting up continues.
6. Bits RTCEN and START are retained.
7. Bits BC[3:0] are initialized.
Rev. 2.00 Sep. 07, 2007 Page 1100 of 1164
REJ09B0321-0200