SH7201 Datasheet, PDF (645/1196 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 13 8-Bit Timers (TMR)
13.8.3 Conflict between TCNT Write and Increment
If a TCNT input clock pulse is generated during the T₂ state of a TCNT write cycle, the write takes
priority and the counter is not incremented as shown in figure 13.13.
TCNT write cycle by CPU
T₁
T₂
Pφ
Address
TCNT address
Internal write signal
TCNT input clock
TCNT
N
M
Counter write data
Figure 13.13 Conflict between TCNT Write and Increment
13.8.4 Conflict between TCOR Write and Compare Match
If a compare match event occurs during the T₂ state of a TCOR write cycle, the TCOR write takes
priority and the compare match signal is inhibited as shown in figure 13.14.
TCOR write cycle by CPU
T₁
T₂
Pφ
Address
TCOR address
Internal write signal
TCNT
N
N+1
TCOR
Compare match signal
N
M
TCOR write data
Inhibited
Figure 13.14 Conflict between TCOR Write and Compare Match
Rev. 2.00 Sep. 07, 2007 Page 617 of 1164
REJ09B0321-0200