SH7201 Datasheet, PDF (144/1196 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 6 Interrupt Controller (INTC)
NMI
IRQ7 to IRQ0
PINT7 to PINT0
UBC
H-UDI
ADC
MTU2
RTC
WDT
IIC3
DMAC
SCIF
RCAN-ET
SSI
TMR
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
Input control
Priority
identifier
Com-
parator
Interrupt
request
SR
I3 I2 I1 I0
CPU
ICR0
ICR2
PINTER
IBCR
ICR1
IRQRR
PIRR
IBNR
IPR
IPR01, IPR02,
IPR05 to IPR16
Module bus
Bus
interface
[Legend]
UBC:
H-UDI:
ADC:
MTU2:
RTC:
WDT:
IIC3:
DMAC:
SCIF:
RCAN-ET:
SSI:
TMR:
User break controller
User debugging interface
A/D converter
Multi-function timer pulse unit 2
Realtime clock
Watchdog timer
I²C bus interface 3
Direct memory access controller
Serial communication interface with FIFO
Controller area network
Serial sound interface
8-bit timer
INTC
ICR0: Interrupt control register 0
ICR1: Interrupt control register 1
ICR2: Interrupt control register 2
IRQRR: IRQ interrupt request register
PINTER: PINT interrupt enable register
PIRR: PINT interrupt request register
IBCR: Bank control register
IBNR: Bank number register
IPR01, IPR02, IPR05 to IPR16:
Interrupt priority registers 01, 02, 05 to 16
Figure 6.1 Block Diagram of INTC
Rev. 2.00 Sep. 07, 2007 Page 116 of 1164
REJ09B0321-0200