SH7201 Datasheet, PDF (776/1196 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 17 I²C Bus Interface 3 (IIC3)
Master transmit mode
SCL
(Master output)
9
SDA
(Master output)
SDA
(Slave output)
A
TDRE
Master receive mode
1
2
3
4
5
6
7
8
9
1
A
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Bit 7
TEND
TRS
RDRF
ICDRS
Data 1
ICDRR
Data 1
User
processing
[1] Clear TDRE after clearing [2] Read ICDRR (dummy read)
TEND and TRS
[3] Read ICDRR
Figure 17.7 Master Receive Mode Operation Timing (1)
Rev. 2.00 Sep. 07, 2007 Page 748 of 1164
REJ09B0321-0200