SH7201 Datasheet, PDF (1181/1196 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Main Revisions and Additions in this Edition
Item
Figure 16.11 Sample Flowchart
for Transmitting Serial Data
Page Revision (See Manual for Details)
716 Modified
Yes
Write transmit data to SCFTDR
and read 1 from TDFE and
TEND flags in SCFSR, then clear
[1]
these flags to 0
No
All data transmitted?
[1] SCIF status check and transmit data write:
Read SCFSR and check that the
TDFE flag is set to 1, then write
transmit data to SCFTDR, and read 1
from the TDFE and TEND flags, then
clear these flags to 0.
Figure 16.16 Sample Flowchart 720
for Transmitting/Receiving Serial
Data
Modified
Yes
Write transmit data to SCFTDR,
and read 1 from TDFE and TEND
flags in SCFTDR, then clear
[1]
these flags to 0
[1] SCIF status check and transmit data
write:
Read SCFSR and check that the
TDFE flag is set to 1, then write
transmit data to SCFTDR, and
read 1 from the TDFE and TEND
flags, then clear these flags to 0.
The transition of the TDFE flag from
Figure 17.22 Bit Synchronous
Circuit Timing
Table 17.5 Time for Monitoring
SCL
764 Figure modified
765 Table modified
CKS3 CKS2
1
0
1
Time for Monitoring SCL*¹
33 tpcyc*²
81 tpcyc*²
17.7.1 Issuance of Stop Condition 766
and Start Condition
(Retransmission)
17.7.2 Settings for Multi-Master 766
Operation
17.7.3 Reading ICDRR in Master
Receive Mode
18.3.1 Control Register (SSICR) 774
Title added
Added
Added
Bit Bit Name
11 SPDP
Description
Serial Padding Polarity
0: Padding bits are low.
1: Padding bits are high.
Note: When MUEN = 1, padding bits are
low. (The MUTE function is given
priority.)
Rev. 2.00 Sep. 07, 2007 Page 1153 of 1164
REJ09B0321-0200