SH7201 Datasheet, PDF (1011/1196 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 24 On-Chip RAM
Section 24 On-Chip RAM
This LSI has an on-chip RAM module that achieves high-speed access and can store instructions
or data.
On-chip RAM operation and write access to the RAM can be enabled or disabled through the
RAM enable bits and RAM write enable bits.
24.1 Features
• Pages
Two pages (pages 0 and 1) are provided.
• Memory map
The on-chip RAM is located in the address spaces shown in table 24.1.
Table 24.1 On-Chip RAM Address Spaces
Page
Page 0
Page 1
Address
H'FFF80000 to H'FFF83FFF
H'FFF84000 to H'FFF87FFF
• Ports
Each page has two independent read and write ports and is connected to the internal bus (I
bus), CPU instruction fetch bus (F bus), and CPU memory access bus (M bus). (Note that the F
bus is connected only to the read ports.)
The F bus and M bus are used for access by the CPU, and the I bus is used for access by the
DMAC via the internal DMA write bus/internal DMA read bus and bus bridge.
• Priority
When requests for access to the same page from different buses coincide, the access is
processed in priority order. The priority is I bus > M bus > F bus.
Rev. 2.00 Sep. 07, 2007 Page 983 of 1164
REJ09B0321-0200