SH7201 Datasheet, PDF (319/1196 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 10 Bus Monitor
10.1.3 Bus Monitor Status Register 2 (SYCBESTS2)
SYCBESTS2 indicates the status of slave buses (external bus/peripheral bus (2)/others) regarding
whether a timeout occurred, whether an illegal address access was made, or which bus master
accessed the slave bus.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
— ETO EER — — — EMST[1:0] — — — — — — — —
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R R R R R R R R R R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
— — OER — — — OMST[1:0] — — SHER — — — SHMST[1:0]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R R R R R R R R R R
Initial
Bit
Bit Name Value
31

0
30
ETO
0
29
EER
0
28 to 26 
All 0
R/W Description
R
Reserved
This bit is always read as 0. The write value should
always be 0.
R
Timeout
This bit indicates that a timeout occurred on the
external bus when the first bus error occurred.
0: Timeout not generated
1: Timeout generated
R
Illegal Address Access
This bit indicates that an illegal address access was
made on the external bus when the first bus error
occurred.
0: Illegal address access not made
1: Illegal address access made
R
Reserved
These bits are always read as 0. The write value
should always be 0.
Rev. 2.00 Sep. 07, 2007 Page 291 of 1164
REJ09B0321-0200