SH7201 Datasheet, PDF (217/1196 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 8 Cache
Initial
Bit
Bit Name Value R/W Description
31 to 17 
All 0
R Reserved
These bits are always read as 0. The write value should
always be 0.
16
LE
0
R/W Lock Enable
Enables or disables the cache locking function.
0: Non-cache locking mode
1: Cache locking mode
15 to 10 
All 0
R Reserved
These bits are always read as 0. The write value should
always be 0.
9
W3LOAD* 0
R/W Way 3 Load
8
W3LOCK 0
R/W Way 3 Lock
When a cache miss occurs by the prefetch instruction
while W3LOAD = 1 and W3LOCK = 1 in cache locking
mode, the data is always loaded into way 3. Under any
other condition, the cache miss data is loaded into the
way to which LRU points.
7 to 2 
All 0
R Reserved
These bits are always read as 0. The write value should
always be 0.
1
W2LOAD* 0
R/W Way 2 Load
0
W2LOCK 0
R/W Way 2 Lock
When a cache miss occurs by the prefetch instruction
while W2LOAD = 1 and W2LOCK =1 in cache locking
mode, the data is always loaded into way 2. Under any
other condition, the cache miss data is loaded into the
way to which LRU points.
Note: * The W3LOAD and W2LOAD bits should not be set to 1 at the same time.
Rev. 2.00 Sep. 07, 2007 Page 189 of 1164
REJ09B0321-0200