SH7201 Datasheet, PDF (353/1196 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 11 Direct Memory Access Controller (DMAC)
Initial
Bit
Bit Name Value
R/W Description
5 to 0 DCTG[5:0] 000000 R/W 011000: SCIF 6ch TX
011001: SCIF 7ch RX
011010: SCIF 7ch TX
011011: SSI 0ch
011100: SSI 1ch
011101: RCAN-ET 0ch
011110: RCAN-ET 1ch
011111: MTU2 0ch
100000: MTU2 1ch
100001: MTU2 2ch
100010: MTU2 3ch
100011: MTU2 4ch
100100: ADC
100101 to 111111: Setting prohibited
Note:
Only write to bits of this register other than the reload function enable bits (BRLOD,
SRLOD, and DRLOD) when a transfer operation is not in process on the corresponding
channel (the corresponding DASTS bit in the DMA arbitration status register (DMASTS) is
"0") and DMA transfer is disabled (DMST in the DMA activation control register (DMSCNT)
or DEN in DMA control register B for the channel (DMCNTBn) is set to "0"). Operation is not
guaranteed if this register is written to when both conditions are not satisfied.
Rev. 2.00 Sep. 07, 2007 Page 325 of 1164
REJ09B0321-0200