SH7201 Datasheet, PDF (1045/1196 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 26 User Debugging Interface (H-UDI)
26.4 Operation
26.4.1 TAP Controller
Figure 26.2 shows the internal states of the TAP controller.
1 Test -logic-reset
0
1
0 Run-test/idle
1
Select-DR
0
1
Capture-DR
0
Shift-DR 0
1
1
Exit1-DR
0
Pause-DR 0
1
0
Exit2-DR
1
Update-DR
1
0
1
Select-IR
0
1
Capture-IR
0
Shift-IR
0
1
1
Exit1-IR
0
Pause-IR 0
1
0
Exit2-IR
1
Update-IR
1
0
Figure 26.2 TAP Controller State Transitions
Note:
The transition condition is the UDTMS value at the rising edge of UDTCK. The UDTDI
value is sampled at the rising edge of UDTCK; shifting occurs at the falling edge of
UDTCK. For details on change timing of the UDTDO value, see section 26.4.3, UDTDO
Output Timing. The UDTDO is at high impedance, except with shift-DR and shift-IR
states. There is a transition to test-logic-reset asynchronously with UDTCK by UDTRST
assertion or deep standby mode.
Rev. 2.00 Sep. 07, 2007 Page 1017 of 1164
REJ09B0321-0200