SH7201 Datasheet, PDF (259/1196 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 9 Bus State Controller (BSC)
9.4.14 SDRAMm Timing Register (SDmTR) (m = 0, 1)
SDmTR specifies the timing for read and write accesses to SDRAM.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
—————————————
DRAS[2:0]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0 ———
R/W: R R R R R R R R R R R R R R/W R/W R/W
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
— — DRCD[1:0]
DPCG[2:0]
DWR — — — — —
DCL[2:0]
Initial value: 0
0 —————— 0
0
0
0
0 ———
R/W: R R R/W R/W R/W R/W R/W R/W R R R R R R/W R/W R/W
Initial
Bit
Bit Name Value
R/W
31 to 19 
All 0
R
18 to 16 DRAS[2:0] Undefined R/W
15, 14 
All 0
R
13, 12 DRCD[1:0] Undefined R/W
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
Row Active Interval Setting
These bits specify the minimum interval that must
elapse between the SDRAM row activation command
(ACT) and deactivation (PRA).
000: 1 cycle
:
111: 8 cycles
Reserved
These bits are always read as 0. The write value
should always be 0.
Row Column Latency Setting
These bits specify the SDRAM row column latency.
00: 1 cycles
01: 2 cycles
10: 3 cycles
11: 4 cycles
Rev. 2.00 Sep. 07, 2007 Page 231 of 1164
REJ09B0321-0200