SH7201 Datasheet, PDF (321/1196 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 10 Bus Monitor
Bit
4 to 2
Bit Name

Initial
Value
All 0
1, 0
SHMST
00
[1:0]
R/W Description
R
Reserved
These bits are always read as 0. The write value
should always be 0.
R
Bus Master
These bits indicate the bus master that accessed
peripheral bus (2) when the first bus error occurred.
00: CPU
01: DMAC (destination side)
10: Setting prohibited
11: DMAC (source side)
Rev. 2.00 Sep. 07, 2007 Page 293 of 1164
REJ09B0321-0200