SH7201 Datasheet, PDF (859/1196 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 19 Controller Area Network (RCAN-ET)
• Requirements of Bit Configuration Register
1-bit time (8 to 25 quanta)
SYNC_SEG
1
PRSEG
PHSEG1
TSEG1
4-16
PHSEG2
TSEG2
2-8
Quantum
SYNC_SEG: Segment for establishing synchronisation of nodes on the CAN bus. (Normal bit
edge transitions occur in this segment.)
PRSEG: Segment for compensating for physical delay between networks.
PHSEG1:
Buffer segment for correcting phase drift (positive). (This segment is extended
when synchronisation (resynchronisation) is established.)
PHSEG2:
Buffer segment for correcting phase drift (negative). (This segment is shortened
when synchronisation (resynchronisation) is established)
TSEG1:
TSG1 + 1
TSEG2:
TSG2 + 1
The RCAN-ET Bit Rate Calculation is:
Bit Rate =
fclk
2 × (BRP + 1) × (TSEG1 + TSEG2 + 1)
where BRP is given by the register value and TSEG1 and TSEG2 are derived values from TSG1
and TSG2 register values.
f_CLK = Peripheral Clock
BCR Setting Constraints
TSEG1min > TSEG2 ≥ SJWmax (SJW = 1 to 4)
8 ≤ TSEG1 + TSEG2 + 1 ≤ 25 time quanta (TSEG1 + TSEG2 + 1 = 7 is not allowed)
TSEG2 ≥ 2
Rev. 2.00 Sep. 07, 2007 Page 831 of 1164
REJ09B0321-0200