SH7201 Datasheet, PDF (363/1196 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 11 Direct Memory Access Controller (DMAC)
11.3.11 DMA Interrupt Control Register (DMICNT)
DMICNT controls DMA interrupts for the respective channels.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DINTM
————————
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R R R R R R R R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
————————————————
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R R R R R R R R R R
Initial
Bit
Bit Name Value
R/W Description
31 to 24 DINTM
All 0
R/W DMA Interrupt Control
These bits are used to control whether DMA transfer
end interrupts for the respective channels should be
generated for the interrupt controller.
When a bit is cleared to "0", interrupt requests for the
corresponding channel are not generated.
When these bits are set to "1", DMA transfer end
interrupts for the corresponding channel are generated
for the interrupt controller.
For details, see section 11.5.2, DMA Interrupt
Requests.
0: Interrupt disabled
1: Interrupt enabled
23 to 0 
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
Note: Bits 31 to 24 correspond to channels 0 to 7, respectively (31: channel 0, 30: channel
1. …24: channel 7).
Rev. 2.00 Sep. 07, 2007 Page 335 of 1164
REJ09B0321-0200