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SH7201 Datasheet, PDF (83/1196 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series | |||
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Section 2 CPU
Instruction
Instruction Code
Operation
Execu-
tion
Cycles
Compatibility
SH2,
T Bit SH2E SH4 SH-2A
STC
SR,Rn
0000nnnn00000010 SR â Rn
2
 Yes Yes Yes
STC
TBR,Rn
0000nnnn01001010 TBR â Rn
1

Yes
STC
GBR,Rn
0000nnnn00010010 GBR â Rn
1
 Yes Yes Yes
STC
VBR,Rn
0000nnnn00100010 VBR â Rn
1
 Yes Yes Yes
STC.L SR,@-Rn
0100nnnn00000011 Rn-4 â Rn, SR â (Rn)
2
 Yes Yes Yes
STC.L GBR,@-Rn
0100nnnn00010011 Rn-4 â Rn, GBR â (Rn)
1
 Yes Yes Yes
STC.L VBR,@-Rn
0100nnnn00100011 Rn-4 â Rn, VBR â (Rn)
1
 Yes Yes Yes
STS
MACH,Rn
0000nnnn00001010 MACH â Rn
1
 Yes Yes Yes
STS
MACL,Rn
0000nnnn00011010 MACL â Rn
1
 Yes Yes Yes
STS
PR,Rn
0000nnnn00101010 PR â Rn
1
 Yes Yes Yes
STS.L MACH,@-Rn 0100nnnn00000010 Rn-4 â Rn, MACH â (Rn) 1
 Yes Yes Yes
STS.L MACL,@-Rn 0100nnnn00010010 Rn-4 â Rn, MACL â (Rn) 1
 Yes Yes Yes
STS.L PR,@-Rn
0100nnnn00100010 Rn-4 â Rn, PR â (Rn)
1
 Yes Yes Yes
TRAPA #imm
11000011iiiiiiii PC/SR â stack area,
5
 Yes Yes Yes
(imm à 4 + VBR) â PC
Notes: 1. Instruction execution cycles: The execution cycles shown in the table are minimums. In
practice, the number of instruction execution states in cases such as the following:
a. When there is a conflict between an instruction fetch and a data access
b. When the destination register of a load instruction (memory â register) is the same
as the register used by the next instruction.
* In the event of bank overflow, the number of cycles is 19.
Rev. 2.00 Sep. 07, 2007 Page 55 of 1164
REJ09B0321-0200
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