SH7201 Datasheet, PDF (264/1196 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 9 Bus State Controller (BSC)
9.4.17 SDRAM Clock Stop Control Signal Setting Register (SDCKSCNT)
SDCKSCNT enables or disables the clock stop control signal (internal signal in the chip) and
specifies the number of assert cycles.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
DCK
SEN
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R R R R R R R R R R/W
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
————————
DCKSC[7:0]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
R/W: R R R R R R R R R/W R/W R/W R/W R/W R/W R/W R/W
Bit
Bit Name
31 to 17 
Initial
Value
All 0
16
DCKSEN 0
15 to 8 
All 0
R/W Description
R
Reserved
These bits are always read as 0. The write value
should always be 0.
R/W Clock Stop Control Signal Enable
This bit is used to enable or disable the clock stop
control signal. When enabled, the clock stop control
signal operates during transition to and from deep-
power-down mode and stops the CKIO (high level).
When disabled, the clock stop control signal stays low
level.
0: Clock stop control signal disabled
1: Clock stop control signal enabled
R
Reserved
These bits are always read as 0. The write value
should always be 0.
Rev. 2.00 Sep. 07, 2007 Page 236 of 1164
REJ09B0321-0200