SH7201 Datasheet, PDF (600/1196 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
(6) Operation when Error Occurs during Normal Mode Operation, and Operation is
Restarted in Reset-Synchronized PWM Mode
Figure 12.130 shows an explanatory diagram of the case where an error occurs in normal mode
and operation is restarted in reset-synchronized PWM mode after re-setting.
1
2
3
Power-on TMDR TOER
reset (normal) (1)
MTU2
module output
4
5
6
TIOR PFC TSTR
(1 init (MTU2) (1)
0 out)
7
8
9
10
Match Error PFC TSTR
occurs (PORT) (0)
11
12
13
TIOR TIOR TOER
(0 init (disabled) (0)
0 out)
14
15
16
17
18
TOCR TMDR TOER PFC TSTR
(RPWM) (1) (MTU2) (1)
TIOC3A
TIOC3B
TIOC3D
Port output
PB16
PB17
High-Z
High-Z
PB19
High-Z
Figure 12.130 Error Occurrence in Normal Mode,
Recovery in Reset-Synchronized PWM Mode
1 to 13 are the same as in figure 12.125.
14. Select the reset-synchronized PWM output level and cyclic output enabling/disabling with
TOCR.
15. Set reset-synchronized PWM.
16. Enable channel 3 and 4 output with TOER.
17. Set MTU2 output with the PFC.
18. Operation is restarted by TSTR.
Rev. 2.00 Sep. 07, 2007 Page 572 of 1164
REJ09B0321-0200