SH7201 Datasheet, PDF (344/1196 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 11 Direct Memory Access Controller (DMAC)
Initial
Bit
Bit Name Value
R/W
23 to 19 
All 0
R
18 to 16 SZSEL[2:0] Undefined R/W
15

0
R
14 to 12 SAMOD
[2:0]
Undefined R/W
11

0
R
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
Transfer Data Size Selection
These bits are used to specify the number of bits
transferred in each single data transfer. The unit for
transfer can be selected as byte (8 bit), word (16 bit),
or longword (32 bit). For details, see section 11.9,
Units of Transfer and Positioning of Bytes for Transfer.
Set the transfer size so that it doesn't exceed the
widths of the data buses supported by the source and
destination for DMA transfer. The bus widths of the
data buses are fixed by hardware.
000: Byte (8 bits)
001: Word (16 bits)
010: Longword (32 bits)
011 to 111: Setting prohibited
Reserved
This bit is always read as 0. The write value should
always be 0.
Source Address Direction Control
These bits are used to specify the direction of counting
for the source address.
000: Fixed
001: Incrementation
010: Decrementation
011: Rotation
100 to 111: Setting prohibited
Reserved
This bit is always read as 0. The write value should
always be 0.
Rev. 2.00 Sep. 07, 2007 Page 316 of 1164
REJ09B0321-0200