SH7201 Datasheet, PDF (86/1196 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 2 CPU
2.4.9 FPU-Related CPU Instructions
Table 2.18 FPU-Related CPU Instructions
Instruction
LDS
Rm,FPSCR
LDS
Rm,FPUL
LDS.L @Rm+, FPSCR
LDS.L @Rm+, FPUL
STS
FPSCR, Rn
STS
FPUL,Rn
STS.L FPSCR,@-Rn
STS.L FPUL,@-Rn
Instruction Code
Operation
Execution
Cycles
T Bit
0100mmmm01101010 Rm→FPSCR
1

0100mmmm01011010 Rm→FPUL
1

0100mmmm01100110 (Rm)→FPSCR, Rm+=4 1

0100mmmm01010110 (Rm)→FPUL, Rm+=4 1

0000nnnn01101010 FPSCR→Rn
1

0000nnnn01011010 FPUL→Rn
1

0100nnnn01100010 Rn-=4, FPSCR→(Rn) 1

0100nnnn01010010 Rn-=4, FPUL→(Rn) 1

Compatibility
SH2E SH4
SH-2A/
SH2A-FPU
Yes Yes Yes
Yes Yes Yes
Yes Yes Yes
Yes Yes Yes
Yes Yes Yes
Yes Yes Yes
Yes Yes Yes
Yes Yes Yes
Rev. 2.00 Sep. 07, 2007 Page 58 of 1164
REJ09B0321-0200