SH7201 Datasheet, PDF (278/1196 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 9 Bus State Controller (BSC)
Function/Operation
Register
Conditions
Power-down
SDPWDCNT • SDRAM access disabled (set in SDRAMCm*¹)
• Auto-refresh enabled (DRFEN = 1)
• Self-refresh disabled (DSFEN/DSFENCI = 0)
• Deep-power-down disabled (DDPD/DDPDCI = 0)
Deep-power-down
SDDPDCNT • SDRAM access disabled (set in SDRAMCm*¹)
• Self-refresh disabled (DSFEN/DSFENCI = 0)
• Auto-refresh disabled (DRFEN = 0)
• Power-down disabled (DPWD/DPWDCI = 0)
Address register settings SD0ADR,
SD1ADR
• Auto-refresh disabled (DRFEN = 0)
• SDRAM access disabled (set in SDRAMCm*¹)
• Self-refresh disabled (DSFEN/DSFENCI = 0)
• Power-down disabled (DPWD/DPWDCI = 0)
• Deep-power-down disabled (DDPD/DDPDCI = 0)
Timing register settings
SD0TR,
SD1TR
• Self-refresh in progress (DSFEN/DSFENCI = 1)
or
• Self-refresh disabled (DSFEN/DSFENCI = 0)
• Auto-refresh disabled (DRFEN = 0)
• SDRAM access disabled (set in SDRAMCm*¹)
Mode register settings
SD0MOD,
SD1MOD*²
• SDRAM access disabled (set in SDRAMCm*¹)
• Self-refresh disabled (DSFEN/DSFENCI = 0)
• Power-down disabled (DPWD/DPWDCI = 0)
• Deep-power-down disabled (DDPD/DDPDCI = 0)
Clock stop control signal SDCKSCNT
settings
• Deep-power-down disabled (DDPD/DDPDCI = 0)
Notes: 1. After writing 0 to EXENB, check to confirm that the EXENB bit has been cleared to 0.
2. Do not fail to confirm that all status bits in the SDRAM status register (SDSTR) have
been cleared to 0 before rewriting this bit.
Rev. 2.00 Sep. 07, 2007 Page 250 of 1164
REJ09B0321-0200