SH7201 Datasheet, PDF (471/1196 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
Table 12.38 TIOC3B Output Level Select Function
Bit 0
OLS1P
0
1
Initial Output
High level
Low level
Active Level
Low level
High level
Function
Compare Match Output
Up Count
Down Count
Low level
High level
High level
Low level
12.3.21 Timer Output Level Buffer Register (TOLBR)
TOLBR is an 8-bit readable/writable register that functions as a buffer for TOCR2 and specifies
the PWM output level in complementary PWM mode and reset-synchronized PWM mode.
Bit: 7
—
Initial value: 0
R/W: R
6
5
4
3
2
1
0
— OLS3N OLS3P OLS2N OLS2P OLS1N OLS1P
0
0
0
0
0
0
0
R R/W R/W R/W R/W R/W R/W
Initial
Bit
Bit Name value R/W Description
7, 6 —
All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
5
OLS3N
0
R/W Specifies the buffer value to be transferred to the
OLS3N bit in TOCR2.
4
OLS3P
0
R/W Specifies the buffer value to be transferred to the
OLS3P bit in TOCR2.
3
OLS2N
0
R/W Specifies the buffer value to be transferred to the
OLS2N bit in TOCR2.
2
OLS2P
0
R/W Specifies the buffer value to be transferred to the
OLS2P bit in TOCR2.
1
OLS1N
0
R/W Specifies the buffer value to be transferred to the
OLS1N bit in TOCR2.
0
OLS1P
0
R/W Specifies the buffer value to be transferred to the
OLS1P bit in TOCR2.
Figure 12.3 shows an example of the PWM output level setting procedure in buffer operation.
Rev. 2.00 Sep. 07, 2007 Page 443 of 1164
REJ09B0321-0200