SH7201 Datasheet, PDF (140/1196 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 5 Exception Handling
Exception Type
Register bank error (underflow)
Trap instruction
Slot illegal instruction
General illegal instruction
Integer division instruction
Stack Status
SP
Start address of relevant
RESBANK instruction
SR
32 bits
32 bits
SP
Address of instruction
after TRAPA instruction
SR
32 bits
32 bits
Jump destination address
SP _{of delayed branch instruction}
SR
32 bits
32 bits
Start address of general
SP
illegal instruction
SR
32 bits
32 bits
Start address of relevant
SP
integer division instruction
SR
32 bits
32 bits
Rev. 2.00 Sep. 07, 2007 Page 112 of 1164
REJ09B0321-0200