SH7201 Datasheet, PDF (23/1196 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

19.3 Mailbox.............................................................................................................................. 811
19.3.1 Mailbox Structure ................................................................................................. 811
19.3.2 Message Control Field .......................................................................................... 813
19.3.3 Local Acceptance Filter Mask (LAFM)................................................................ 817
19.3.4 Message Data Fields ............................................................................................. 818
19.4 RCAN-ET Control Registers ............................................................................................. 819
19.4.1 Master Control Register (MCR) ........................................................................... 819
19.4.2 General Status Register (GSR) ............................................................................. 825
19.4.3 Bit Configuration Register (BCR0, BCR1) .......................................................... 828
19.4.4 Interrupt Request Register (IRR) .......................................................................... 833
19.4.5 Interrupt Mask Register (IMR) ............................................................................. 839
19.4.6 Transmit Error Counter (TEC) and Receive Error Counter (REC)....................... 840
19.5 RCAN-ET Mailbox Registers............................................................................................ 841
19.5.1 Transmit Pending Register (TXPR0, TXPR1)...................................................... 842
19.5.2 Transmit Cancel Register 0 (TXCR0) .................................................................. 845
19.5.3 Transmit Acknowledge Register 0 (TXACK0) .................................................... 846
19.5.4 Abort Acknowledge Register 0 (ABACK0) ......................................................... 847
19.5.5 Data Frame Receive Pending Register 0 (RXPR0)............................................... 848
19.5.6 Remote Frame Receive Pending Register 0 (RFPR0) .......................................... 849
19.5.7 Mailbox Interrupt Mask Register 0 (MBIMR0).................................................... 850
19.5.8 Unread Message Status Register 0 (UMSR0)....................................................... 851
19.6 Application Note................................................................................................................ 852
19.6.1 Configuration of RCAN-ET ................................................................................. 852
19.6.2 Test Mode Settings ............................................................................................... 857
19.6.3 Message Transmission Sequence.......................................................................... 859
19.6.4 Message Receive Sequence .................................................................................. 861
19.6.5 Reconfiguration of Mailbox.................................................................................. 863
19.7 Interrupt Sources................................................................................................................ 865
19.8 CAN Bus Interface............................................................................................................. 867
19.9 Usage Notes ....................................................................................................................... 868
19.9.1 Module Standby Mode.......................................................................................... 868
19.9.2 Reset ..................................................................................................................... 868
19.9.3 CAN Sleep Mode.................................................................................................. 868
19.9.4 Register Access..................................................................................................... 868
19.9.5 Interrupts............................................................................................................... 869
Section 20 A/D Converter (ADC)......................................................................871
20.1 Features.............................................................................................................................. 871
20.2 Input/Output Pins ............................................................................................................... 873
20.3 Register Configuration....................................................................................................... 874
Rev. 2.00 Sep. 07, 2007 Page xxiii of xxviii