SH7201 Datasheet, PDF (129/1196 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 5 Exception Handling
5.3 Address Errors
5.3.1 Address Error Sources
Address errors occur when instructions are fetched or data read or written, as shown in table 5.7.
Table 5.7 Bus Cycles and Address Errors
Bus Cycle
Type
Bus
Master
Bus Cycle Description
Address Errors
Instruction
fetch
CPU
Instruction fetched from even address
Instruction fetched from odd address
None (normal)
Address error occurs
Instruction fetched from area other than
H'F0000000 to H'F5FFFFFFF in cache
address array space*¹
None (normal)
Instruction fetched from H'F0000000 to
H'F5FFFFFFF in cache address array
space*¹
Address error occurs
Data
read/write
CPU
Word data accessed from even address
Word data accessed from odd address
None (normal)
Address error occurs
Longword data accessed from a
longword boundary
None (normal)
Longword data accessed from other than Address error occurs
a long-word boundary
Byte or word data accessed in on-chip
peripheral module space*²
None (normal)
Longword data accessed in 16-bit on-
chip peripheral module space*²
None (normal)
Longword data accessed in 8-bit on-chip None (normal)
peripheral module space*²
Notes: 1. For details on cache address array space, see section 8, Cache.
2. For details on peripheral module space, see section 9, Bus State Controller (BSC).
Rev. 2.00 Sep. 07, 2007 Page 101 of 1164
REJ09B0321-0200