SH7201 Datasheet, PDF (738/1196 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 16 Serial Communication Interface with FIFO (SCIF)
• Receiving Serial Data (Asynchronous Mode)
Figures 16.6 and 16.7 show sample flowcharts for serial reception.
Use the following procedure for serial data reception after enabling the SCIF for reception.
Start of reception
Read ER, DR, BRK flags in
SCFSR and ORER
[1]
flag in SCLSR
Yes
ER, DR, BRK or ORER = 1?
[1] Receive error handling and break detection:
Read the DR, ER, and BRK flags in SCFSR, and the
ORER flag in SCLSR, to identify any error, perform the
appropriate error handling, then clear the DR, ER,
BRK, and ORER flags to 0. In the case of a framing
error, a break can also be detected by reading the
value of the RxD pin.
No
Error handling ^{[2] SCIF status check and receive data read:}
Read SCFSR and check that RDF = 1, then read the
Read RDF flag in SCFSR
[2]
receive data in SCFRDR, read 1 from the RDF flag,
and then clear the RDF flag to 0. The transition of the
No
RDF = 1?
RDF flag from 0 to 1 can also be identified by an RXI
interrupt.
[3] Serial reception continuation procedure:
Yes
To continue serial reception, read at least the receive
Read receive data in
SCFRDR, and clear RDF
flag in SCFSR to 0
trigger set number of receive data bytes from
SCFRDR, read 1 from the RDF flag, then clear the
RDF flag to 0. The number of receive data bytes in
SCFRDR can be ascertained by reading from
No
All data received?
[3]
SCRFDR.
Yes
Clear RE bit in SCSCR to 0
End of reception
Figure 16.6 Sample Flowchart for Receiving Serial Data
Rev. 2.00 Sep. 07, 2007 Page 710 of 1164
REJ09B0321-0200