SH7201 Datasheet, PDF (12/1196 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

6.3.7 PINT Interrupt Request Register (PIRR) .............................................................. 126
6.3.8 Bank Control Register (IBCR).............................................................................. 127
6.3.9 Bank Number Register (IBNR) ............................................................................ 128
6.3.10 DMA Transfer Request Enable Register 0 (DREQER0) ...................................... 129
6.3.11 DMA Transfer Request Enable Register 1 (DREQER1) ...................................... 130
6.3.12 DMA Transfer Request Enable Register 2 (DREQER2) ...................................... 131
6.3.13 DMA Transfer Request Enable Register 3 (DREQER3) ...................................... 132
6.4 Interrupt Sources................................................................................................................ 133
6.4.1 NMI Interrupt........................................................................................................ 133
6.4.2 User Break Interrupt ............................................................................................. 133
6.4.3 H-UDI Interrupt .................................................................................................... 133
6.4.4 IRQ Interrupts....................................................................................................... 134
6.4.5 PINT Interrupts..................................................................................................... 135
6.4.6 On-Chip Peripheral Module Interrupts ................................................................. 135
6.5 Interrupt Exception Handling Vector Table and Priority................................................... 136
6.6 Operation ........................................................................................................................... 146
6.6.1 Interrupt Operation Sequence ............................................................................... 146
6.6.2 Stack after Interrupt Exception Handling ............................................................. 148
6.7 Interrupt Response Time.................................................................................................... 149
6.8 Register Banks ................................................................................................................... 154
6.8.1 Register Banks and Bank Control Registers ......................................................... 155
6.8.2 Bank Save and Restore Operations....................................................................... 155
6.8.3 Save and Restore Operations after Saving to All Banks....................................... 157
6.8.4 Register Bank Exception ...................................................................................... 158
6.8.5 Register Bank Error Exception Handling ............................................................. 158
6.9 Data Transfer with Interrupt Request Signals.................................................................... 159
6.9.1 Handling Interrupt Request Signals as Sources for
CPU Interrupt but not DMAC Activation............................................................. 159
6.9.2 Handling Interrupt Request Signals as Sources for
DMAC Activation but not CPU Interrupt............................................................. 159
6.10 Usage Note......................................................................................................................... 160
6.10.1 Timing to Clear an Interrupt Source ..................................................................... 160
Section 7 User Break Controller (UBC)............................................................ 161
7.1 Features.............................................................................................................................. 161
7.2 Input/Output Pin ................................................................................................................ 163
7.3 Register Descriptions......................................................................................................... 163
7.3.1 Break Address Register (BAR)............................................................................. 164
7.3.2 Break Address Mask Register (BAMR) ............................................................... 165
7.3.3 Break Data Register (BDR) .................................................................................. 166
Rev. 2.00 Sep. 07, 2007 Page xii of xxviii