SH7201 Datasheet, PDF (374/1196 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 11 Direct Memory Access Controller (DMAC)
Unit operand transfer
DMA request
Interrupt
DTEND
Transfer data
Operand 1
Byte count
Operand 2
Operand 3
Sequential operand transfer
Channel arbitration
Channel arbitration
DMA request
Interrupt
DTEND
Transfer data
Operand 1
Byte count
Operand 2
Operand 3
Non-stop transfer
DMA request
Interrupt
DTEND
Transfer data
Channel arbitration
Channel arbitration
Byte count
Figure 11.3 DMA Transfer Conditions
Relations between the mode and conditions of DMA transfer are shown in table 11.6.
Rev. 2.00 Sep. 07, 2007 Page 346 of 1164
REJ09B0321-0200