SH7201 Datasheet, PDF (24/1196 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

20.3.1 A/D Data Registers A to H (ADDRA to ADDRH) .............................................. 874
20.3.2 A/D Control/Status Register (ADCSR) ................................................................ 876
20.4 Operation ........................................................................................................................... 880
20.4.1 Single Mode.......................................................................................................... 880
20.4.2 Multi Mode ........................................................................................................... 883
20.4.3 Scan Mode ............................................................................................................ 885
20.4.4 A/D Converter Activation by External Trigger, MTU2, or TMR......................... 888
20.4.5 Input Sampling and A/D Conversion Time .......................................................... 888
20.4.6 External Trigger Input Timing.............................................................................. 890
20.5 Interrupt Sources and DMAC Transfer Request ................................................................ 891
20.6 Definitions of A/D Conversion Accuracy.......................................................................... 891
20.7 Usage Notes ....................................................................................................................... 893
20.7.1 Module Standby Mode Setting ............................................................................. 893
20.7.2 Setting Analog Input Voltage ............................................................................... 893
20.7.3 Notes on Board Design ......................................................................................... 893
20.7.4 Processing of Analog Input Pins........................................................................... 894
20.7.5 Permissible Signal Source Impedance .................................................................. 895
20.7.6 Influences on Absolute Precision.......................................................................... 896
20.7.7 Usage Note when Shifting to Single Mode during A/D Conversion .................... 896
Section 21 D/A Converter (DAC) ..................................................................... 897
21.1 Features.............................................................................................................................. 897
21.2 Input/Output Pins............................................................................................................... 898
21.3 Register Descriptions......................................................................................................... 898
21.3.1 D/A Data Registers 0 and 1 (DADR0 and DADR1)............................................. 899
21.3.2 D/A Control Register (DACR) ............................................................................. 899
21.4 Operation ........................................................................................................................... 901
21.5 Usage Notes ....................................................................................................................... 902
21.5.1 Module Standby Mode Setting ............................................................................. 902
21.5.2 D/A Output Hold Function in Software Standby Mode........................................ 902
21.5.3 D/A Conversion and D/A Output in Deep Standby Mode.................................... 902
21.5.4 Setting Analog Input Voltage ............................................................................... 902
Section 22 I/O Ports........................................................................................... 903
22.1 Port A................................................................................................................................. 903
22.1.1 Register Configuration.......................................................................................... 904
22.1.2 Port A Data Registers H and L (PADRH and PADRL)........................................ 904
22.1.3 Port A Port Registers H and L (PAPRH and PAPRL).......................................... 906
22.2 Port B ................................................................................................................................. 907
22.2.1 Register Configuration.......................................................................................... 908
Rev. 2.00 Sep. 07, 2007 Page xxiv of xxviii