SH7201 Datasheet, PDF (285/1196 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 9 Bus State Controller (BSC)
Multiple read
CKIO
SDRAM command
ACT RD
RD
RD
RD PRA
Data bus
d0
d1
d2
d3
ACT: Row and bank activation command
RD: Read command
PRA: Precharge-all command
Figure 9.14 Multiple Read Timing Example (Multiple Read of 4 Data Units,
Shortest Timing Settings) Consecutive Read Commands Issued
Multiple write
CKIO
SDRAM command
ACT WR WR WR WR PRA
Data bus
d0
d1
d2
d3
ACT: Row and bank activation command
WR: Write command
PRA: Precharge-all command
Figure 9.15 Multiple Write Timing Example (Multiple Write of 4 Data Units,
Shortest Timing Settings) Consecutive Write Commands Issued
Multiple read
CKIO
SDRAM command
Data bus
ACT RD DSL RD DSL RD DSL RD PRA
d0
d1
d2
d3
ACT: Row and bank activation command
RD: Read command
PRA: Precharge-all command
DSL: Deselect command
Figure 9.16 Multiple Read Timing Example (Multiple Read of 4 Data Units,
Shortest Timing Settings) Non-Consecutive Read Commands Issued
Rev. 2.00 Sep. 07, 2007 Page 257 of 1164
REJ09B0321-0200