SH7201 Datasheet, PDF (348/1196 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 11 Direct Memory Access Controller (DMAC)
Table 11.3 shows the DMA source/destination address registers. For details on the rotation address
"indexing" mode, see section 11.11, Rotate Function. Note that when performing pipelined
transfer to or from external devices and modules that support burst access, make sure to set the
direction bits to select address incrementation ("001") or rotation ("011").
Table 11.3 Increment/Decrement for DMA Source/Destination Address Registers
Transfer data size
selection bits
"000"
SZSEL
(fixed)
"000" (8 bits)
±0
"001" (16 bits)
±0
"010" (32 bits)
±0
Address Indexing Mode
SAMOD or DAMOD
"001"
"010"
"011"
(plus direction) (minus direction) (rotation)
+1
−1
+1
+2
−2
+2
+4
−4
+4
11.3.8 DMA Control Register A (DMCNTA)
DMCNTA handles the selections of the transfer mode and the condition of transfer, control of
reload functions, and selection of DMA sources.
Bit: 31
—
Initial value: 0
R/W: R
Bit: 15
—
Initial value: 0
R/W: R
30 29 28 27 26 25 24 23
— MDSEL[1:0] — — DSEL[1:0] —
0
0
0
0
R R/W R/W R
0
0
0
0
R R/W R/W R
14 13 12 11 10 9
8
7
— — — — BRLOD SRLOD DRLOD —
0
0
0
0
0
0
0
0
R R R R R/W R/W R/W R
22 21 20 19 18 17 16
— — — — — STRG[1:0]
0
0
0
0
0
0
0
R R R R R R/W R/W
6
5
4
3
2
1
0
—
DCTG[5:0]
0
0
0
0
0
0
0
R R/W R/W R/W R/W R/W R/W
Bit
31, 30
Bit Name

Initial
Value
All 0
R/W Description
R
Reserved
These bits are always read as 0. The write value
should always be 0.
Rev. 2.00 Sep. 07, 2007 Page 320 of 1164
REJ09B0321-0200