SH7201 Datasheet, PDF (582/1196 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
12.7.9 Contention between TGR Read and Input Capture
If an input capture signal is generated in the T1 state of a TGR read cycle, the data that is read will
be the data in the buffer before input capture transfer for channels 0 to 4, and the data after input
capture transfer for channel 5.
Figures 12.114 and 12.115 show the timing in this case.
TGR read cycle
T1 T2
Pφ
Address
TGR address
Read signal
Input capture
signal
TGR
N
M
Internal data
bus
N
Figure 12.114 Contention between TGR Read and Input Capture (Channels 0 to 4)
TGR read cycle
T1 T2
Pφ
Address
TGR address
Read signal
Input capture
signal
TGR
N
M
Internal data
bus
M
Figure 12.115 Contention between TGR Read and Input Capture (Channel 5)
Rev. 2.00 Sep. 07, 2007 Page 554 of 1164
REJ09B0321-0200