SH7201 Datasheet, PDF (414/1196 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
Table 12.10 TPSC1 and TPSC0 (Channel 5)
Bit 1
Channel TPSC1
Bit 0
TPSC0
Description
5
0
0
Internal clock: counts on Pφ/1
1
Internal clock: counts on Pφ/4
1
0
Internal clock: counts on Pφ/16
1
Internal clock: counts on Pφ/64
Note: Bits 7 to 2 are reserved in channel 5. These bits are always read as 0. The write value
should always be 0.
12.3.2 Timer Mode Register (TMDR)
The TMDR registers are 8-bit readable/writable registers that are used to set the operating mode of
each channel. The MTU2 has five TMDR registers, one each for channels 0 to 4. TMDR register
settings should be changed only when TCNT operation is stopped.
Bit: 7
—
Initial value: 0
R/W: R
6
5
4
3
2
1
0
BFE BFB BFA
MD[3:0]
0
0
0
0
0
0
0
R/W R/W R/W R/W R/W R/W R/W
Initial
Bit
Bit Name Value R/W Description
7
—
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
6
BFE
0
R/W Buffer Operation E
Specifies whether TGRE_0 and TGRF_0 are to operate
in the normal way or to be used together for buffer
operation.
When TGRF is used as a buffer register, TGRF
compare match is generated.
In channels 1 to 4, this bit is reserved. It is always read
as 0 and the write value should always be 0.
0: TGRE_0 and TGRF_0 operate normally
1: TGRE_0 and TGRF_0 used together for buffer
operation
Rev. 2.00 Sep. 07, 2007 Page 386 of 1164
REJ09B0321-0200