SH7201 Datasheet, PDF (630/1196 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 13 8-Bit Timers (TMR)
Initial
Bit
Bit Name Value R/W Description
6
CMIEA
0
R/W Compare Match Interrupt Enable A
Selects whether CMFA interrupt requests (CMIA) are
enabled or disabled when the CMFA flag in TCSR is
set to 1.
0: CMFA interrupt requests (CMIA) are disabled
1: CMFA interrupt requests (CMIA) are enabled
5
OVIE
0
R/W Timer Overflow Interrupt Enable
Selects whether OVF interrupt requests (OVI) are
enabled or disabled when the OVF flag in TCSR is set
to 1.
0: OVF interrupt requests (OVI) are disabled
1: OVF interrupt requests (OVI) are enabled
4, 3 CCLR[1:0] 00
R/W Counter Clear 1 and 0*
These bits select the method by which TCNT is
cleared.
00: Clearing is disabled
01: Cleared by compare match A
10: Cleared by compare match B
11: Cleared at rising edge (TMRIS in TCCR is cleared
to 0) of the external reset input or when the external
reset input is high (TMRIS in TCCR is set to 1)
2 to 0 CKS[2:0]
000
R/W Clock Select 2 to 0*
These bits select the clock input to TCNT and count
condition. See table 13.2.
Note: * To use an external reset or external clock, the function of the corresponding pin should
be selected using the pin function controller (PFC). For details, see section 23, Pin
Function Controller (PFC).
Rev. 2.00 Sep. 07, 2007 Page 602 of 1164
REJ09B0321-0200