SH7201 Datasheet, PDF (595/1196 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
Figure 12.125 shows an explanatory diagram of the case where an error occurs in normal mode
and operation is restarted in normal mode after re-setting.
1
2
3
Power-on TMDR TOER
reset (normal) (1)
MTU2
module output
4
5
6
TIOR PFC TSTR
(1 init (MTU2) (1)
0 out)
7
Match
8
9
10
11
12
13
14
Error PFC TSTR TMDR TIOR PFC TSTR
occurs (PORT) (0) (normal) (1 init (MTU2) (1)
0 out)
TIOC*A
TIOC*B
Port output
PB, PC, PD*¹
High-Z
PB, PC, PD*²
High-Z
Notes: 1. This pin is multiplexed with TIOC*A.
2. This pin is multiplexed with TIOC*B.
Figure 12.125 Error Occurrence in Normal Mode, Recovery in Normal Mode
1. After a power-on reset, MTU2 output is low and ports are in the high-impedance state.
2. After a power-on reset, the TMDR setting is for normal mode.
3. For channels 3 and 4, enable output with TOER before initializing the pins with TIOR.
4. Initialize the pins with TIOR. (The example shows initial high output, with low output on
compare-match occurrence.)
5. Set MTU2 output with the PFC.
6. The count operation is started by TSTR.
7. Output goes low on compare-match occurrence.
8. An error occurs.
9. Set port output with the PFC and output the inverse of the active level.
10. The count operation is stopped by TSTR.
11. Not necessary when restarting in normal mode.
12. Initialize the pins with TIOR.
13. Set MTU2 output with the PFC.
14. Operation is restarted by TSTR.
Rev. 2.00 Sep. 07, 2007 Page 567 of 1164
REJ09B0321-0200