SH7201 Datasheet, PDF (286/1196 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 9 Bus State Controller (BSC)
CKIO
Multiple write
SDRAM command
Data bus
ACT WR DSL WR DSL WR DSL WR PRA
d0
d1
d2
d3
ACT: Row and bank activation command
WR: Write command
PRA: Precharge-all command
DSL: Deselect command
Figure 9.17 Multiple Write Timing Example (Multiple Write of 4 Data Units,
Shortest Timing Settings) Non-Consecutive Write Commands Issued
Multiple write
CKIO
SDRAM command
Data bus
ACT WR WR WR PRA ACT WR PRA
d0
d1
d2
d3
Row address A
ACT: Row and bank activation command
WR: Write command
PRA: Precharge-all command
Row address B
Figure 9.18 Multiple Write Timing Example (Multiple Write of 4 Data Units,
Shortest Timing Settings) Access Spanning Rows
Rev. 2.00 Sep. 07, 2007 Page 258 of 1164
REJ09B0321-0200