SH7201 Datasheet, PDF (175/1196 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 6 Interrupt Controller (INTC)
Program
execution state
Interrupt?
Yes
NMI?
Yes
No
No
User break?
Yes
Read exception
handling vector table
Save SR to stack
Copy accept-interrupt
level to I3 to I0
Save PC to stack
Branch to interrupt
exception service routine
No
H-UDI
No
interrupt?
Yes
Yes
No
Level 15
interrupt?
Yes
Level 14
No
interrupt?
I3 to I0 ≤
level 14?
No
Yes
I3 to I0 ≤
level 13?
Level 1
No
interrupt?
Yes
No _Yes
I3 to I0 =
level 0?
No
Figure 6.2 Interrupt Operation Flow
Rev. 2.00 Sep. 07, 2007 Page 147 of 1164
REJ09B0321-0200