SH7201 Datasheet, PDF (180/1196 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 6 Interrupt Controller (INTC)
Interrupt acceptance
2 Icyc + 3 Bcyc + 1 Pcyc
3 Icyc + m1 + m2
3 Icyc
m1 m2 m3
IRQ
Instruction (instruction replacing
interrupt exception handling)
First instruction in
interrupt service routine
[Legend]
m1: Vector address read
m2: Saving of SR (stack)
m3: Saving of PC (stack)
F D E EMMME
FDE
Figure 6.6 Example of Pipeline Operation when IRQ Interrupt is Accepted
(Register Banking without Register Bank Overflow)
2 Icyc + 3 Bcyc + 1 Pcyc
IRQ
9 Icyc
3 Icyc + m1 + m2
RESBANK instruction
Instruction (instruction replacing
interrupt exception handling)
First instruction in
interrupt service routine
FDEEEEEEEEE
m1 m2 m3
D E EMMME
FD
[Legend]
m1: Vector address read
m2: Saving of SR (stack)
m3: Saving of PC (stack)
Interrupt acceptance
Figure 6.7 Example of Pipeline Operation when Interrupt is Accepted during RESBANK
Instruction Execution (Register Banking without Register Bank Overflow)
Rev. 2.00 Sep. 07, 2007 Page 152 of 1164
REJ09B0321-0200