SH7201 Datasheet, PDF (113/1196 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 4 Clock Pulse Generator (CPG)
Bit
6 to 4
3
2 to 0
Bit Name
IFC[2:0]
Initial
Value
000
RNGS
0
PFC[2:0] 011
R/W Description
R/W Internal Clock Frequency Division Ratio
These bits specify the frequency division ratio of the
internal clock with respect to the output frequency of
PLL circuit 1.
000: × 1 time
001: × 1/2 time
010: × 1/3 time
011: × 1/4 time
100: × 1/6 time
101: × 1/8 time
R/W Output Range Select for PLL Circuit 1
When the multiplication ratio for the PLL circuit 1 is
specified to × 3, set this bit according to the output
frequency of the PLL circuit 1.
0: Low frequency mode
(Output frequency of the PLL circuit 1 is equal to
or smaller than 120 MHz.)
1: High frequency mode
(Multiplication ratio for the PLL circuit 1 is specified
to × 3 and its output frequency exceeds 120 MHz.)
R/W Peripheral Clock Frequency Division Ratio
These bits specify the frequency division ratio of the
peripheral clock with respect to the output frequency
of PLL circuit 1.
000: × 1 time
001: × 1/2 time
010: × 1/3 time
011: × 1/4 time
100: × 1/6 time
101: × 1/8 time
110: × 1/12 time
Rev. 2.00 Sep. 07, 2007 Page 85 of 1164
REJ09B0321-0200