SH7201 Datasheet, PDF (66/1196 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 2 CPU
2.4 Instruction Set
2.4.1 Instruction Set by Classification
Table 2.10 lists the instructions according to their classification.
Table 2.10 Classification of Instructions
Classification
Data transfer
Types
13
Operation
Code
MOV
MOVA
MOVI20
MOVI20S
MOVML
MOVMU
MOVRT
MOVT
MOVU
NOTT
PREF
SWAP
XTRCT
Function
Data transfer
Immediate data transfer
Peripheral module data transfer
Structure data transfer
Reverse stack transfer
Effective address transfer
20-bit immediate data transfer
20-bit immediate data transfer
8-bit left-shit
R0–Rn register save/restore
Rn–R14 and PR register save/restore
T bit inversion and transfer to Rn
T bit transfer
Unsigned data transfer
T bit inversion
Prefetch to operand cache
Swap of upper and lower bytes
Extraction of the middle of registers
connected
No. of
Instructions
62
Rev. 2.00 Sep. 07, 2007 Page 38 of 1164
REJ09B0321-0200