SH7201 Datasheet, PDF (767/1196 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 17 I²C Bus Interface 3 (IIC3)
Initial
Bit
Bit Name Value R/W Description
5
RDRF
0
R/W Receive Data Register Full
[Clearing conditions]
• When 0 is written in RDRF after reading RDRF = 1
• When ICDRR is read
[Setting condition]
• When a receive data is transferred from ICDRS to
ICDRR
4
NACKF
0
R/W No Acknowledge Detection Flag
[Clearing condition]
• When 0 is written in NACKF after reading NACKF
=1
[Setting condition]
• When no acknowledge is detected from the receive
device in transmission while the ACKE bit in ICIER
is 1
3
STOP
0
R/W Stop Condition Detection Flag
[Clearing condition]
• When 0 is written in STOP after reading STOP = 1
[Setting conditions]
• In master mode, when a stop condition is detected
after frame transfer
• In slave mode, when the slave address in the first
byte, after detecting start condition, matches the
address set in SAR, and then the stop condition is
detected
Rev. 2.00 Sep. 07, 2007 Page 739 of 1164
REJ09B0321-0200