SH7201 Datasheet, PDF(1183/1196 Page) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

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SH7201 Datasheet, PDF (1183/1196 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

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Main Revisions and Additions in this Edition

Item

Page Revision (See Manual for Details)

19.6.1 Configuration of RCAN-ET 856 Modified

(4) CAN sleep mode

â¢ Don't set MCR5 (Sleep Mode) without entering Halt

Mode.

â¢ After setting MCR1, make sure that GSR4 is set and

the RCAN-ET has entered Halt Mode before clearing

MCR1.

20.7.7 Usage Note when Shifting 896

to Single Mode during A/D

Conversion

Added

25.2.9 Deep Standby Oscillation 999 Notes added

Settling Clock Select Register

(DSCNT)

Bit Bit Name Description

2 to 0 CKS[2:0] Clock Select

:

Setting

value

Clock

select

000:

001:

010:

011:

100:

1 Ã PÏ*1

1/64 Ã PÏ*1

1/128 Ã PÏ*1

1/256 Ã PÏ*2

1/512 Ã PÏ*2

25.2.10 Deep Standby Cancel

Source Flag Register (DSFR)

Notes: 1. Do not use this setting.

2. Set the clock so that it is equal to or longer than the

oscillation settling time 2 on return from standby

(tOSC3).

1000, Added

1001 Note: * Only 0 can be written after reading 1 to clear the

flag.

Even when IRQ is input after a manual reset

has been accepted as a source canceling deep

standby, the IRQ flag is not set.

25.4.1 Note on Setting Registers 1011 Title added

25.4.2 Note on Canceling Standby 1011 Added

Mode when an External Clock is

being Input

Rev. 2.00 Sep. 07, 2007 Page 1155 of 1164

REJ09B0321-0200

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