SH7201 Datasheet, PDF (230/1196 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 9 Bus State Controller (BSC)
CS6 to CS0
RD
WR3 to WR0
WAIT
Area
controller
(CSC)
CSMODn
CS1WCNTn
CS2WCNTn
A27 to A0
BC3 to BC0
D31 to D0
Access
controller
CSnCNT
CSnREC
SDCmCNT
SDCS1, SDCS0
SDRAS, SDCAS
SDWE, SDCKE
DQM3 to DQM0
SDRAM
controller
(SDRAMC)
SDRFCNT0/1 SDPWDCNT
SDIR0/1
SDDPWDCNT
SDmADR SDSTR
SDmTR
SDCKSCNT
SDmMOD
[Legend]
CSMODn: CSn mode register
CS1WCNTn: CSn wait control register 1
CS2WCNTn: CSn wait control register 2
CSnCNT:
CSn control register
CSnREC:
CSn recovery cycle setting register
SDCmCNT: SDRAMCm control register
SDRFCNT0/1: SDRAM refresh control register 0/1
SDIR0/1:
SDRAM initialization register 0/1
SDmADR: SDRAMm address register
SDmTR:
SDRAMm timing register
SDmMOD: SDRAMm mode register
SDPWDCNT: SDRAM power-down control register
SDDPWDCNT: SDRAM deep-power-down control register
SDSTR:
SDRAM status register
SDCKSCNT: SDRAM clock stop control signal setting register
Note: n = 0 to 6, m = 0 and 1
Figure 9.1 Block Diagram of BSC
Rev. 2.00 Sep. 07, 2007 Page 202 of 1164
REJ09B0321-0200