SH7201 Datasheet, PDF (552/1196 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
(4) Complementary PWM Mode Output Protection Function
Complementary PWM mode output has the following protection functions.
(a) Register and counter miswrite prevention function
With the exception of the buffer registers, which can be rewritten at any time, access by the CPU
can be enabled or disabled for the mode registers, control registers, compare registers, and
counters used in complementary PWM mode by means of the RWE bit in the timer read/write
enable register (TRWER). The applicable registers are some (21 in total) of the registers in
channels 3 and 4 shown in the following:
• TCR_3 and TCR_4, TMDR_3 and TMDR_4, TIORH_3 and TIORH_4, TIORL_3 and
TIORL_4, TIER_3 and TIER_4, TCNT_3 and TCNT_4, TGRA_3 and TGRA_4, TGRB_3
and TGRB_4, TOER, TOCR, TGCR, TCDR, and TDDR.
This function enables miswriting due to CPU runaway to be prevented by disabling CPU access to
the mode registers, control registers, and counters. When the applicable registers are read in the
access-disabled state, undefined values are returned. Writing to these registers is ignored.
Rev. 2.00 Sep. 07, 2007 Page 524 of 1164
REJ09B0321-0200