SH7201 Datasheet, PDF (1180/1196 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Main Revisions and Additions in this Edition
Item
11.1 Features
15.3.15 Year Alarm Register
(RYRAR)
15.5.1 Register Writing during
RTC Count
Page Revision (See Manual for Details)
302 Modified
1. Single data transfer: Transfer in one read cycle and one
write cycle by the DMAC (in the case of dual address
transfer), and one read cycle or one write cycle transfer by
the DMAC (at single address transfer)
2. Single operand transfer: Continuous data transfer by the
DMAC on one channel (amount of data to be transferred is
set in a register)
:
6. BIU: Bus Interface Unit (peripheral module). One of the
following four kinds according to the source or destination of
transfer.
BIU_E: External space (normal space and SDRAM
space)
BIU_P: Peripheral bus (1) (see figure 1.1)
BIU_SH: Peripheral bus (2) (see figure 1.1), on-chip
RAM space
BIU_C: Peripheral bus (3) (see figure 1.1)
652 Added
RYRAR is an alarm register corresponding to the year
counter RYRCNT. The assignable range is from 0000
through 9999 (practically in BCD), otherwise operation
errors occur. RYRAR is not initialized by a power-on
reset, a manual reset, or in deep standby mode or
software standby mode.
661 Modified
Do not write to the count registers (RSECCNT,
RMINCNT, RHRCNT, RDAYCNT, RWKCNT,
RMONCNT, and RYRCNT) during the RTC counting
(while the START bit in RCR2 is 1). If any of the count
registers is written to during the RTC counting, the
count register may not be read correctly immediately
after the execution of a write instruction. The RTC
counting must be stopped before writing to any of the
count registers.
Rev. 2.00 Sep. 07, 2007 Page 1152 of 1164
REJ09B0321-0200