SH7201 Datasheet, PDF (1019/1196 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 25 Power-Down Modes
25.2.3 Standby Control Register 3 (STBCR3)
STBCR3 is an 8-bit readable/writable register that controls the operation of modules in power-
down modes. STBCR3 is initialized to H'3F by a power-on reset or in deep standby mode but
retains its previous value by a manual reset or in software standby mode. Only byte access is valid.
Note: When writing to this register, see section 25.4, Usage Note.
Bit: 7

Initial value: 0
R/W: R
6
5
4
3
2
1
0

MSTP
35

MSTP MSTP MSTP
33 32 31

0
1
1
1
1
1
1
R R/W R R/W R/W R/W R
Initial
Bit
Bit Name Value R/W Description
7, 6

All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
5
MSTP35 1
R/W Module Stop 35
When the MSTP35 bit is set to 1, the supply of the
clock to the MTU2 is halted.
0: MTU2 runs.
1: Clock supply to MTU2 halted.
4

1
R
Reserved
This bit is always read as 1. The write value should
always be 1.
3
MSTP33 1
R/W Module Stop 33
When the MSTP33 bit is set to 1, the supply of the
clock to the TMR is halted.
0: TMR runs.
1: Clock supply to TMR halted.
2
MSTP32 1
R/W Module Stop 32
When the MSTP32 bit is set to 1, the supply of the
clock to the ADC is halted.
0: ADC runs.
1: Clock supply to ADC halted.
Rev. 2.00 Sep. 07, 2007 Page 991 of 1164
REJ09B0321-0200