SH7201 Datasheet, PDF (237/1196 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 9 Bus State Controller (BSC)
Register Name
Abbreviation R/W
SDRAM power-down control SDPWDCNT R/W
register
SDRAM deep-power-down
control register
SDDPWDCNT R/W
SDRAM0 address register
SD0ADR
R/W
SDRAM0 timing register
SD0TR
R/W
SDRAM0 mode register
SD0MOD
R/W
SDRAM1 address register
SD1ADR
R/W
SDRAM1 timing register
SD1TR
R/W
SDRAM1 mode register
SD1MOD
R/W
SDRAM status register
SDSTR
R/W
SDRAM clock stop control
signal setting register
SDCKSCNT R/W
AC characteristics switching ACSWR
R/W
register
Note: * Depends on the setting of the MD pin.
Initial Value Address
Access
Size
H'00000000 H'FF422010 8, 16, 32
H'00000000 H'FF422014 8, 16, 32
H'00000x0x
H'000xxx0x
H'0000xxxx
H'00000x0x
H'000xxx0x
H'0000xxxx
H'00000000
H'0000000F
H'FF422020
H'FF422024
H'FF422028
H'FF422040
H'FF422044
H'FF422048
H'FF4220E4
H'FF4220E8
8, 16, 32
8, 16, 32
16, 32
8, 16, 32
8, 16, 32
16, 32
8, 16, 32
8, 16, 32
H'00000000 H'FFFD8808 8, 16, 32
9.4.1 CSn Control Register (CSnCNT) (n = 0 to 6)
CSnCNT selects the width of the external bus and controls the operation of the CSC interface.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
— — — — — — — — — — BSIZE[1:0] — — — EXENB
Initial value: 0
0
0
0
0
0
0
0
0
0
0*¹ 0*¹ 0
0
0
0 *²
R/W: R R R R R R R R R R R/W R/W R R R R/W
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
————————————————
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R R R R R R R R R R
Bit
Bit Name
31 to 22 
Initial
Value
All 0
R/W Description
R
Reserved
These bits are always read as 0. The write value
should always be 0.
Rev. 2.00 Sep. 07, 2007 Page 209 of 1164
REJ09B0321-0200